diff options
author | Determinant <ted.sybil@gmail.com> | 2017-11-11 00:14:16 -0500 |
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committer | Determinant <ted.sybil@gmail.com> | 2017-11-11 00:14:16 -0500 |
commit | 42b7d024c3b5e8d76cbf091cec12ee9ab732628a (patch) | |
tree | 5ffaa30d9536eb4dbb832abb030db4aaa9842967 /src/memory.rs | |
parent | 9eba033073c5c11c441f1ddd573af8c7f006ac2c (diff) |
finish most part of ppu
Diffstat (limited to 'src/memory.rs')
-rw-r--r-- | src/memory.rs | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/memory.rs b/src/memory.rs new file mode 100644 index 0000000..386e859 --- /dev/null +++ b/src/memory.rs @@ -0,0 +1,39 @@ +pub trait VMem { + fn read(&self, addr: u16) -> u8; + fn write(&mut self, addr: u16, data: u8); +} + +pub struct CPUMemory { + internal: [u8; 2048] +} + +impl CPUMemory { + pub fn new() -> Self { + CPUMemory{internal: [0; 2048]} + } +} + +impl VMem for CPUMemory { + fn read(&self, addr: u16) -> u8 { + if addr < 0x2000 { + self.internal[(addr & 0x07ff) as usize] + } else if addr < 0x4000 { + match addr & 0x7 { + _ => 0 + } + } else { + panic!("invalid memory read access at 0x{:04x}", addr) + } + } + fn write(&mut self, addr: u16, data: u8) { + if addr < 0x2000 { + self.internal[(addr & 0x07ff) as usize] = data; + } else if addr < 0x4000 { + match addr & 0x7 { + _ => () + } + } else { + panic!("invalid memory write access at 0x{:04x}", addr) + } + } +} |