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authorDeterminant <ted.sybil@gmail.com>2017-11-17 00:30:28 -0500
committerDeterminant <ted.sybil@gmail.com>2017-11-17 00:30:28 -0500
commit0157d11bfc1f0cb01815f75bbf80635f71910b4c (patch)
treebc8743ed76030ae932917ab85165913cb09e3950 /src/memory.rs
parent35061de86daee3ed46f4a6ba14983672424dce56 (diff)
pass the vbl nmi timing test
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/memory.rs b/src/memory.rs
index fc8732c..f8b6632 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -68,7 +68,13 @@ impl<'a> VMem for CPUMemory<'a> {
unsafe{(*self.sram.get())[(addr & 0x07ff) as usize] = data;}
} else if addr < 0x4000 {
match addr & 0x7 {
- 0x0 => ppu.write_ctl(data),
+ 0x0 => {
+ let old = ppu.get_flag_nmi();
+ ppu.write_ctl(data);
+ if !old && ppu.try_nmi() && ppu.vblank {
+ cpu.trigger_delayed_nmi()
+ } /* toggle NMI flag can generate multiple ints */
+ },
0x1 => ppu.write_mask(data),
0x3 => ppu.write_oamaddr(data),
0x4 => ppu.write_oamdata(data),