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authorDeterminant <ted.sybil@gmail.com>2017-11-16 19:22:46 -0500
committerDeterminant <ted.sybil@gmail.com>2017-11-16 19:22:46 -0500
commit35061de86daee3ed46f4a6ba14983672424dce56 (patch)
tree107adffbe4fb8cfb5e855cbbabe59a37dc2e4b40 /src/memory.rs
parent904c18222ec50929aa8f6b397ff0b90ec47d97a4 (diff)
...
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs20
1 files changed, 7 insertions, 13 deletions
diff --git a/src/memory.rs b/src/memory.rs
index c302af9..fc8732c 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -21,7 +21,7 @@ pub struct CPUMemory<'a> {
}
impl<'a> CPUMemory<'a> {
- pub fn new(ppu: *mut PPU<'a>,
+ pub fn new(ppu: &mut PPU<'a>,
mapper: &'a VMem,
ctl1: Option<&'a Controller>,
ctl2: Option<&'a Controller>) -> Self {
@@ -50,14 +50,8 @@ impl<'a> VMem for CPUMemory<'a> {
}
} else if addr < 0x4020 {
match addr {
- 0x4016 => match self.ctl1 {
- Some(c) => c.read(),
- None => 0
- },
- 0x4017 => match self.ctl2 {
- Some(c) => c.read(),
- None => 0
- },
+ 0x4016 => if let Some(c) = self.ctl1 { c.read() } else { 0 },
+ 0x4017 => if let Some(c) = self.ctl2 { c.read() } else { 0 },
_ => 0
}
} else if addr < 0x6000 {
@@ -86,10 +80,10 @@ impl<'a> VMem for CPUMemory<'a> {
} else if addr < 0x4020 {
match addr {
0x4014 => ppu.write_oamdma(data, cpu),
- 0x4016 => match self.ctl1 {
- Some(c) => c.write(data),
- None => ()
- },
+ 0x4016 => {
+ if let Some(c) = self.ctl1 { c.write(data) }
+ if let Some(c) = self.ctl2 { c.write(data) }
+ }
_ => ()
}
} else if addr < 0x6000 {