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authorDeterminant <ted.sybil@gmail.com>2017-11-16 00:29:42 -0500
committerDeterminant <ted.sybil@gmail.com>2017-11-16 00:29:42 -0500
commitea9cfd9e1c6672d55370d8475a99f5def4b11752 (patch)
tree379872f30502ca78f4e58fba1ab963d22f00b12e /src/memory.rs
parentf2ff1e431129877d4b2093546a6864b474ed2219 (diff)
support basic 1p controller
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs28
1 files changed, 25 insertions, 3 deletions
diff --git a/src/memory.rs b/src/memory.rs
index 6b960ec..c302af9 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -2,6 +2,7 @@
use ppu::PPU;
use mos6502::CPU;
use cartridge::{MirrorType, Cartridge};
+use controller::Controller;
use core::cell::{UnsafeCell, Cell};
use core::ptr::null_mut;
@@ -14,15 +15,20 @@ pub struct CPUMemory<'a> {
sram: UnsafeCell<[u8; 2048]>,
ppu: Cell<*mut PPU<'a>>,
cpu: Cell<*mut CPU<'a>>,
- mapper: &'a VMem
+ mapper: &'a VMem,
+ ctl1: Option<&'a Controller>,
+ ctl2: Option<&'a Controller>
}
impl<'a> CPUMemory<'a> {
- pub fn new(ppu: *mut PPU<'a>, mapper: &'a VMem) -> Self {
+ pub fn new(ppu: *mut PPU<'a>,
+ mapper: &'a VMem,
+ ctl1: Option<&'a Controller>,
+ ctl2: Option<&'a Controller>) -> Self {
CPUMemory{sram: UnsafeCell::new([0; 2048]),
cpu: Cell::new(null_mut()),
ppu: Cell::new(ppu),
- mapper}
+ mapper, ctl1, ctl2}
}
pub fn init(&self, cpu: *mut CPU<'a>) {
@@ -42,6 +48,18 @@ impl<'a> VMem for CPUMemory<'a> {
0x7 => ppu.read_data(),
_ => 0
}
+ } else if addr < 0x4020 {
+ match addr {
+ 0x4016 => match self.ctl1 {
+ Some(c) => c.read(),
+ None => 0
+ },
+ 0x4017 => match self.ctl2 {
+ Some(c) => c.read(),
+ None => 0
+ },
+ _ => 0
+ }
} else if addr < 0x6000 {
0
} else {
@@ -68,6 +86,10 @@ impl<'a> VMem for CPUMemory<'a> {
} else if addr < 0x4020 {
match addr {
0x4014 => ppu.write_oamdma(data, cpu),
+ 0x4016 => match self.ctl1 {
+ Some(c) => c.write(data),
+ None => ()
+ },
_ => ()
}
} else if addr < 0x6000 {