add mapper and cartridge

5 files changed, 71 insertions, 2 deletions

diff --git a/src/cartridge.rs b/src/cartridge.rs
new file mode 100644
index 0000000..28928c0
--- /dev/null
+++ b/src/cartridge.rs
@@ -0,0 +1,10 @@
+pub enum BankType {
+    PRG_ROM, /* program rom */
+    CHR_ROM, /* pattern rom */
+    SRAM,    /* save ram */
+}
+
+pub trait Cartridge {
+    fn get_bank_num(&self, kind: BankType) -> usize;
+    fn get_bank(&self, idx: usize, kind: BankType) -> *mut [u8];
+}
diff --git a/src/lib.rs b/src/lib.rs
index d38ba01..93ddf74 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -2,3 +2,5 @@ extern crate core;
 mod memory;
 mod mos6502;
 mod ppu;
+mod cartridge;
+mod mapper;
diff --git a/src/main.rs b/src/main.rs
index e429932..4a963b6 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,7 +1,9 @@
 extern crate core;
 mod memory;
-mod ppu;
 mod mos6502;
+mod ppu;
+mod cartridge;
+mod mapper;
 fn main() {
     /*
     let code = [0xa9, 0x01, 0x8d, 0x00, 0x02, 0xa9, 0x05, 0x8d, 0x01, 0x02, 0xa9, 0x08, 0x8d, 0x02, 0x02 ];
diff --git a/src/mapper.rs b/src/mapper.rs
new file mode 100644
index 0000000..d83157a
--- /dev/null
+++ b/src/mapper.rs
@@ -0,0 +1,55 @@
+use memory::VMem;
+use cartridge::{Cartridge, BankType};
+pub struct Mapper2<'a, T: 'a> where T: Cartridge {
+    cart: &'a T,
+    prg_bank1: &'a [u8],
+    prg_bank2: &'a [u8],
+    chr_bank: &'a mut [u8],
+    sram: &'a mut [u8],
+    bank_num: usize
+}
+
+impl<'a, T> VMem for Mapper2<'a, T> where T: Cartridge {
+    fn read(&self, addr: u16) -> u8 {
+        let addr = addr as usize;
+        if addr < 0x2000 {
+            self.chr_bank[addr]
+        } else if addr >= 0xc000 {
+            self.prg_bank2[addr - 0xc000]
+        } else if addr >= 0x8000 {
+            self.prg_bank1[addr - 0x8000]
+        } else if addr >= 0x6000 {
+            self.sram[addr - 0x6000]
+        } else {
+            panic!("unmapped address: 0x{:04x}", addr)
+        }
+    }
+
+    fn write(&mut self, addr: u16, data: u8) {
+        let addr = addr as usize;
+        if addr < 0x2000 {
+            self.chr_bank[addr] = data;
+        } else if addr >= 0x8000 {
+            self.prg_bank1 = unsafe {&*self.cart.get_bank(
+                data as usize % self.bank_num, BankType::PRG_ROM)};
+        } else if addr >= 0x6000 {
+            self.sram[addr - 0x6000] = data;
+        } else {
+            panic!("invalid write to address: 0x{:04x}", addr);
+        }
+    }
+}
+
+impl<'a, T> Mapper2<'a, T>  where T: Cartridge {
+    fn new(cart: &'a mut T) -> Self {
+        let bank_num = cart.get_bank_num(BankType::PRG_ROM);
+        unsafe {
+            Mapper2{cart,
+                    prg_bank1: &*cart.get_bank(0, BankType::PRG_ROM),
+                    prg_bank2: &*cart.get_bank(bank_num - 1, BankType::PRG_ROM),
+                    chr_bank: &mut *cart.get_bank(0, BankType::CHR_ROM),
+                    sram: &mut *cart.get_bank(0, BankType::SRAM),
+                    bank_num}
+        }
+    }
+}
diff --git a/src/memory.rs b/src/memory.rs
index 386e859..852b837 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -13,7 +13,7 @@ impl CPUMemory {
     }
 }
 
-impl VMem for CPUMemory {
+impl<'a> VMem for CPUMemory {
     fn read(&self, addr: u16) -> u8 {
         if addr < 0x2000 {
             self.internal[(addr & 0x07ff) as usize]