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-rw-r--r--src/tim.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/tim.rs b/src/tim.rs
index 02e65bd..bede8af 100644
--- a/src/tim.rs
+++ b/src/tim.rs
@@ -22,18 +22,22 @@ impl<'a> Timer<'a> {
self.0.arr.write(|w| w.arr().bits(arr));
}
+ #[inline]
pub fn is_enabled(&self) -> bool {
self.0.cr1.read().cen() == tim1::cr1::CENR::ENABLED
}
+ #[inline]
pub fn reset(&self) {
self.0.cnt.write(|w| w.cnt().bits(0));
}
+ #[inline]
pub fn go(&self) {
self.0.cr1.modify(|_, w| w.cen().enabled());
}
+ #[inline]
pub fn stop(&self) {
self.0.cr1.modify(|_, w| w.cen().disabled());
}