diff options
author | Determinant <[email protected]> | 2017-10-18 23:51:44 -0400 |
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committer | Determinant <[email protected]> | 2017-10-18 23:51:44 -0400 |
commit | 3ac3ae705079895e1072470502ffacdb6d2d9bc4 (patch) | |
tree | 4af2b3ca2c7cb9e2a68f38b87c44c56de011593f /src/tim.rs | |
parent | d09fadccb157c47c10a2edfbb3b229dda53a0ee1 (diff) |
add timer impl
Diffstat (limited to 'src/tim.rs')
-rw-r--r-- | src/tim.rs | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/tim.rs b/src/tim.rs new file mode 100644 index 0000000..efbd786 --- /dev/null +++ b/src/tim.rs @@ -0,0 +1,34 @@ +use stm32f103xx::{tim2, TIM2}; + +pub struct Timer<'a> (pub &'a tim2::RegisterBlock); + +impl<'a> Timer<'a> { + pub fn init(&self, timeout: u32) { + let tim = self.0; + self.set_timeout(timeout); + tim.cr1.write(|w| unsafe { + w.opm().continuous() + .cms().bits(0b00) + .dir().up()}); + tim.dier.modify(|_, w| w.uie().set_bit()); + } + + pub fn set_timeout(&self, timeout: u32) { + let psc: u16 = (timeout / (1 << 16)) as u16; + let arr: u16 = (timeout / (psc + 1) as u32) as u16; + self.0.psc.write(|w| w.psc().bits(psc)); + self.0.arr.write(|w| w.arr().bits(arr)); + } + + pub fn reset(&self) { + self.0.cnt.write(|w| w.cnt().bits(0)); + } + + pub fn go(&self) { + self.0.cr1.modify(|_, w| w.cen().enabled()); + } + + pub fn stop(&self) { + self.0.cr1.modify(|_, w| w.cen().disabled()); + } +} |