1 files changed, 11 insertions, 5 deletions

diff --git a/src/tim.rs b/src/tim.rs
index efbd786..02e65bd 100644
--- a/src/tim.rs
+++ b/src/tim.rs
@@ -1,4 +1,4 @@
-use stm32f103xx::{tim2, TIM2};
+use stm32f103xx::{tim1, tim2, TIM2};
 
 pub struct Timer<'a> (pub &'a tim2::RegisterBlock);
 
@@ -6,10 +6,12 @@ impl<'a> Timer<'a> {
     pub fn init(&self, timeout: u32) {
         let tim = self.0;
         self.set_timeout(timeout);
-        tim.cr1.write(|w| unsafe {
-                          w.opm().continuous()
-                           .cms().bits(0b00)
-                           .dir().up()});
+        tim.cr1.write(|w| w.opm().continuous());
+        /* UEV to reload the psc and arr (without an interrupt) */
+        tim.egr.write(|w| w.ug().set_bit());
+        /* clear the interrupt flag caused by UG */
+        tim.sr.modify(|_, w| w.uif().clear());
+        /* finally enable the interrupt trigger */
         tim.dier.modify(|_, w| w.uie().set_bit());
     }
 
@@ -20,6 +22,10 @@ impl<'a> Timer<'a> {
         self.0.arr.write(|w| w.arr().bits(arr));
     }
 
+    pub fn is_enabled(&self) -> bool {
+        self.0.cr1.read().cen() == tim1::cr1::CENR::ENABLED
+    }
+
     pub fn reset(&self) {
         self.0.cnt.write(|w| w.cnt().bits(0));
     }