From e2ccf6053d58a2a478814f4a26018989f6fa0f26 Mon Sep 17 00:00:00 2001 From: Determinant Date: Fri, 17 Nov 2017 13:05:25 -0500 Subject: add test roms --- testroms/branch_timing_tests/1.Branch_Basics.nes | Bin 0 -> 16400 bytes testroms/branch_timing_tests/2.Backward_Branch.nes | Bin 0 -> 16400 bytes testroms/branch_timing_tests/3.Forward_Branch.nes | Bin 0 -> 16400 bytes testroms/branch_timing_tests/readme.txt | 74 +++++++++++++ testroms/nestest.nes | Bin 0 -> 24592 bytes testroms/vbl_nmi_timing/1.frame_basics.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/2.vbl_timing.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/3.even_odd_frames.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/4.vbl_clear_timing.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/5.nmi_suppression.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/6.nmi_disable.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/7.nmi_timing.nes | Bin 0 -> 16400 bytes testroms/vbl_nmi_timing/readme.txt | 118 +++++++++++++++++++++ 13 files changed, 192 insertions(+) create mode 100644 testroms/branch_timing_tests/1.Branch_Basics.nes create mode 100644 testroms/branch_timing_tests/2.Backward_Branch.nes create mode 100644 testroms/branch_timing_tests/3.Forward_Branch.nes create mode 100644 testroms/branch_timing_tests/readme.txt create mode 100644 testroms/nestest.nes create mode 100644 testroms/vbl_nmi_timing/1.frame_basics.nes create mode 100644 testroms/vbl_nmi_timing/2.vbl_timing.nes create mode 100644 testroms/vbl_nmi_timing/3.even_odd_frames.nes create mode 100644 testroms/vbl_nmi_timing/4.vbl_clear_timing.nes create mode 100644 testroms/vbl_nmi_timing/5.nmi_suppression.nes create mode 100644 testroms/vbl_nmi_timing/6.nmi_disable.nes create mode 100644 testroms/vbl_nmi_timing/7.nmi_timing.nes create mode 100644 testroms/vbl_nmi_timing/readme.txt diff --git a/testroms/branch_timing_tests/1.Branch_Basics.nes b/testroms/branch_timing_tests/1.Branch_Basics.nes new file mode 100644 index 0000000..e7f81f0 Binary files /dev/null and b/testroms/branch_timing_tests/1.Branch_Basics.nes differ diff --git a/testroms/branch_timing_tests/2.Backward_Branch.nes b/testroms/branch_timing_tests/2.Backward_Branch.nes new file mode 100644 index 0000000..6e02064 Binary files /dev/null and b/testroms/branch_timing_tests/2.Backward_Branch.nes differ diff --git a/testroms/branch_timing_tests/3.Forward_Branch.nes b/testroms/branch_timing_tests/3.Forward_Branch.nes new file mode 100644 index 0000000..4e701b2 Binary files /dev/null and b/testroms/branch_timing_tests/3.Forward_Branch.nes differ diff --git a/testroms/branch_timing_tests/readme.txt b/testroms/branch_timing_tests/readme.txt new file mode 100644 index 0000000..1f05e8e --- /dev/null +++ b/testroms/branch_timing_tests/readme.txt @@ -0,0 +1,74 @@ +NES 6502 Branch Timing Test ROMs +-------------------------------- +These ROMs test timing of the branch instruction, including edge cases +which an emulator might get wrong. When run on a NES they all give a +passing result. Each ROM runs several tests and reports the result on +screen and by beeping a number of times. See below for the meaning of +failure codes for each test. THE TESTS MUST BE RUN (*AND* *PASS*) IN +ORDER, because some earlier ROMs test things that later ones assume will +work properly. + +Source code for each test is included, and most tests are clearly +divided into sections. Support code is also included, but it runs on a +custom devcart and assembler so it will require some effort to assemble. +Contact me if you'd like assistance porting them to your setup. + + +Branch Timing Summary +--------------------- +An untaken branch takes 2 clocks. A taken branch takes 3 clocks. A taken +branch that crosses a page takes 4 clocks. Page crossing occurs when the +high byte of the branch target address is different than the high byte +of address of the next instruction: + +branch_target: + ... + bne branch_target +next_instruction: + nop + ... +branch_target: + + +1.Branch_Basics +--------------- +Tests branch timing basics and PPU NMI timing, which is needed for the +tests + +2) NMI period is too short +3) NMI period is too too long +4) Branch not taken is too long +5) Branch not taken is too short +6) Branch taken is too long +7) Branch taken is too short + + +2.Backward_Branch +----------------- +Tests backward (negative) branch timing. + +2) Branch from $E4FD to $E4FC is too long +3) Branch from $E4FD to $E4FC is too short +4) Branch from $E5FE to $E5FD is too long +5) Branch from $E5FE to $E5FD is too short +6) Branch from $E700 to $E6FF is too long +7) Branch from $E700 to $E6FF is too short +8) Branch from $E801 to $E800 is too long +9) Branch from $E801 to $E800 is too short + + +3.Forward_Branch +---------------- +Tests forward (positive) branch timing. + +2) Branch from $E5FC to $E5FF is too long +3) Branch from $E5FC to $E5FF is too short +4) Branch from $E6FD to $E700 is too long +5) Branch from $E6FD to $E700 is too short +6) Branch from $E7FE to $E801 is too long +7) Branch from $E7FE to $E801 is too short +8) Branch from $E8FF to $E902 is too long +9) Branch from $E8FF to $E902 is too short + +-- +Shay Green diff --git a/testroms/nestest.nes b/testroms/nestest.nes new file mode 100644 index 0000000..fc2a88c Binary files /dev/null and b/testroms/nestest.nes differ diff --git a/testroms/vbl_nmi_timing/1.frame_basics.nes b/testroms/vbl_nmi_timing/1.frame_basics.nes new file mode 100644 index 0000000..8eece87 Binary files /dev/null and b/testroms/vbl_nmi_timing/1.frame_basics.nes differ diff --git a/testroms/vbl_nmi_timing/2.vbl_timing.nes b/testroms/vbl_nmi_timing/2.vbl_timing.nes new file mode 100644 index 0000000..3a45ec8 Binary files /dev/null and b/testroms/vbl_nmi_timing/2.vbl_timing.nes differ diff --git a/testroms/vbl_nmi_timing/3.even_odd_frames.nes b/testroms/vbl_nmi_timing/3.even_odd_frames.nes new file mode 100644 index 0000000..535cb44 Binary files /dev/null and b/testroms/vbl_nmi_timing/3.even_odd_frames.nes differ diff --git a/testroms/vbl_nmi_timing/4.vbl_clear_timing.nes b/testroms/vbl_nmi_timing/4.vbl_clear_timing.nes new file mode 100644 index 0000000..939f452 Binary files /dev/null and b/testroms/vbl_nmi_timing/4.vbl_clear_timing.nes differ diff --git a/testroms/vbl_nmi_timing/5.nmi_suppression.nes b/testroms/vbl_nmi_timing/5.nmi_suppression.nes new file mode 100644 index 0000000..5677690 Binary files /dev/null and b/testroms/vbl_nmi_timing/5.nmi_suppression.nes differ diff --git a/testroms/vbl_nmi_timing/6.nmi_disable.nes b/testroms/vbl_nmi_timing/6.nmi_disable.nes new file mode 100644 index 0000000..75a3a2c Binary files /dev/null and b/testroms/vbl_nmi_timing/6.nmi_disable.nes differ diff --git a/testroms/vbl_nmi_timing/7.nmi_timing.nes b/testroms/vbl_nmi_timing/7.nmi_timing.nes new file mode 100644 index 0000000..f777a9c Binary files /dev/null and b/testroms/vbl_nmi_timing/7.nmi_timing.nes differ diff --git a/testroms/vbl_nmi_timing/readme.txt b/testroms/vbl_nmi_timing/readme.txt new file mode 100644 index 0000000..03728ec --- /dev/null +++ b/testroms/vbl_nmi_timing/readme.txt @@ -0,0 +1,118 @@ +NTSC NES PPU VBL/NMI Timing Tests +--------------------------------- +These ROMs test the timing of the VBL flag and NMI to an accuracy of a +single PPU clock, and also check special cases. They have been tested on +an actual NES and all give a passing result. Sometimes the NES starts up +with a different PPU timing that causes some of the tests to fail; these +tests don't check that timing arrangement. + +Each ROM runs several tests and reports the result on screen and by +beeping a number of times. See below for the meaning of failure codes +for each test. It's best to run the tests in order, because later ROMs +depend on things tested by earlier ROMs and will give erroneous results +if any earlier ones failed. + +Source code for each test is included, and most tests are clearly +divided into sections. Support code is also included, but it runs on a +custom devcart and assembler so it will require some effort to assemble. +Contact me if you'd like assistance porting them to your setup. + + +1.frame_basics +-------------- +Tests basic VBL flag operation and general timing of PPU frames. + +2) VBL flag isn't being set +3) VBL flag should be cleared after being read +4) PPU frame with BG enabled is too short +5) PPU frame with BG enabled is too long +6) PPU frame with BG disabled is too short +7) PPU frame with BG disabled is too long + + +2.vbl_timing +------------ +Tests timing of VBL being set, and special case where reading VBL flag +as it would be set causes it to not be set for that frame. + +2) Flag should read as clear 3 PPU clocks before VBL +3) Flag should read as set 0 PPU clocks after VBL +4) Flag should read as clear 2 PPU clocks before VBL +5) Flag should read as set 1 PPU clock after VBL +6) Flag should read as clear 1 PPU clock before VBL +7) Flag should read as set 2 PPU clocks after VBL +8) Reading 1 PPU clock before VBL should suppress setting + + +3.even_odd_frames +----------------- +Test clock skipped when BG is enabled on odd PPU frames. Tests +enable/disable BG during 5 consecutive frames, then see how many clocks +were skipped. Patterns are shown as XXXXX, where each X can either be B +(BG enabled) or - (BG disabled). + +2) Pattern ----- should not skip any clocks +3) Pattern BB--- should skip 1 clock +4) Pattern B--B- (one even, one odd) should skip 1 clock +5) Pattern -B--B (one odd, one even) should skip 1 clock +6) Pattern BB-BB (two pairs) should skip 2 clocks + + +4.vbl_clear_timing +------------------ +Tests timing of VBL flag clearing. + +2) Cleared 3 or more PPU clocks too early +3) Cleared 2 PPU clocks too early +4) Cleared 1 PPU clock too early +5) Cleared 3 or more PPU clocks too late +6) Cleared 2 PPU clocks too late +7) Cleared 1 PPU clock too late + + +5.nmi_suppression +----------------- +Tests timing of NMI suppression when reading VBL flag just as it's set, +and that this doesn't occur when reading one clock before or after. + +2) Reading flag 3 PPU clocks before set shouldn't suppress NMI +3) Reading flag when it's set should suppress NMI +4) Reading flag 3 PPU clocks after set shouldn't suppress NMI +5) Reading flag 2 PPU clocks before set shouldn't suppress NMI +6) Reading flag 1 PPU clock after set should suppress NMI +7) Reading flag 4 PPU clocks after set shouldn't suppress NMI +8) Reading flag 4 PPU clocks before set shouldn't suppress NMI +9) Reading flag 1 PPU clock before set should suppress NMI +10)Reading flag 2 PPU clocks after set shouldn't suppress NMI + + +6.nmi_disable +------------- +Tests NMI occurrence when disabling NMI just as VBL flag is set, and +just after. + +2) NMI shouldn't occur when disabled 0 PPU clocks after VBL +3) NMI should occur when disabled 3 PPU clocks after VBL +4) NMI shouldn't occur when disabled 1 PPU clock after VBL +5) NMI should occur when disabled 4 PPU clocks after VBL +6) NMI shouldn't occur when disabled 1 PPU clock before VBL +7) NMI should occur when disabled 2 PPU clocks after VBL + + +7.nmi_timing +------------ +Tests timing of NMI and immediate occurrence when enabled with VBL flag +already set. + +2) NMI occurred 3 or more PPU clocks too early +3) NMI occurred 2 PPU clocks too early +4) NMI occurred 1 PPU clock too early +5) NMI occurred 3 or more PPU clocks too late +6) NMI occurred 2 PPU clocks too late +7) NMI occurred 1 PPU clock too late +8) NMI should occur if enabled when VBL already set +9) NMI enabled when VBL already set should delay 1 instruction +10)NMI should be possible multiple times in VBL + +-- +Shay Green (swap to e-mail) -- cgit v1.2.3-70-g09d2